Flip Chip Test Wafer Pac 2.0

Wafer specifications

  • 6“ silicon wafer
    – other substrates / semiconductor materials
    – on request (e.g. glass, GaAs)

General data

chip no chips size / mm pitch / µm pad configuration I/O’s chips per wafer
1 10,0 x 10,0 200 peripheral 184 28
2 300 peripheral 120 28
3 200/400 area 572 24
4 250 staggered 248 24
5 100 peripheral 378 28

Bump specifications

Available with following bump types

  • Electroless Ni/Au (5μm, 10μm, 15μm and 25μm)
    for ACF, NCP and ICA adhesive Flip Chip attach
  • Solder bumps
    – SnPb 63/37, SnAg4Cu0,5
    – other alloys on request (e.g. PbSn 90/10, AuSn 80/20)

Electrical measurements

  • Daisy Chain Structures
  • Four Point Kelvin Structures

Download design rules geometrical data FC Test Wafer Pac 2.0

PAC-TECH-Test-Chip-2-0 (.pdf/ 1.2MB)