Thinning the die can benefit electronic devices in several ways: reducing thermal resistance, improving device performance, increasing reliability, and lowering overall package height, minimizing die stress, which occurs due to mismatches in the coefficient of thermal expansion (CTE) between the silicon die and the board materials.

The most common technology for wafer thinning is mechanical grinding. Silicon is removed from the backside of the wafer using a two-step process: coarse grinding followed by fine grinding. This is performed using a grinding tool that contains diamond particles of specific dimensions. During coarse grinding, typically 90% of the back grind is completed, significantly reducing the thickness of the wafer. Coarse grinding will cause micro-cracks and damage the silicon lattice. Fine grinding completes the back grind process and removes part of this damage.

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Incoming Wafer Requirements:
General Rules for Wafer Thinning:
Capabilities and Specifications:

PacTech routinely handles bumped wafers of wide-ranging bump heights and pitches and stocks a diverse assortment of front side tapes to provide the best protection for your wafers during processing.