Pac Tech uses an electroless nickel plating process to deposit the Under-Bump-Metallurgy (UBM) and three different technologies to deposit / rework the solder spheres:
The choice between these solder deposition technologies is based on product type, bump height requirements, pad pitch, and volumes to be bumped.
The process flow for a standard wafer level bumping process used at all four Pac Tech manufacturing sites is:
- Incoming logistics: unpackage and prepare work instructions
- Incoming wafer inspection
- Electroless Nickel UBM deposition (see e-Ni section of this web site for more details)
- Flux and Solder deposition (one of three methods described above)
- Wafer clean
- Metrology (bump shear, bump height, yield inspection,…)
- Outgoing wafer inspection
- Outgoing logistics: package and submit paperwork (reports, data files, …)
Flip Chip Bumping and WLCSP Bumping Overview:
Wafer bumping is often separated into two different categories: flip chip bumping (FC) and wafer level chip scale packaging (WLCSP). This categorization and affiliated nomenclature is partially based on the solder bump size and the type of equipment used to create the bump.
“Flip Chip” refers to bumps on semiconductor wafers which are in the range of 50 to 200 µm in height and are usually assembled using and underfill material between the die and the substrate.
“WLCSP” refers to bumps that are in the range of 200 to 500 µm in height and are usually assembled without and underfill material.
The basic flow for each of these technologies is to first deposit a barrier metal on top of the bond pad of the wafer (Under-Bump Metallization or UBM) followed by deposition of the solder.
Common solder alloys offered by Pac Tech include:
SnAgCu (SAC305, SAC405, SAC105)
PbSn 95/5, PbSn 90/10